1. Field
The present invention relates to self-testing electronic modules and, more particularly, to self-testing electronic memory modules.
2. Description of the Related Art
The failure of memory components in an electronic system may result in the loss of valid data. Therefore, it is important to ensure proper memory operation in an electronic system. Memory integrated circuits (“memory chips”) often go through a series of tests at various stages of system manufacture. Once memory chips are deployed in a system, they also generally go through a system level memory test each time the system is booted. In addition, memory chips may undergo a parity checking process during normal system operation.
There are typically at least three test phases which memories undergo during system manufacture. Each phase generally tests for memory defects and for the correct operation of the input/output interface. The first test phase is typically conducted by the memory chip manufacturer and generally involves checking for bit failures, correct memory access speed, etc. The second test phase is typically done by memory module manufacturers and generally involves testing the signal quality, the noise susceptibility, and the operational speed of the memory module as a single unit. The second test phase may also include checking for bit failures in individual memory chips. The third phase is usually carried out by the system manufacturer. During the third phase, the interaction of the memory subsystem with other components in the system is tested. During the third phase, the individual memory module operation is also tested again and the memory array is checked for defects. Because of the significant amount of testing that memories undergo during the manufacturing process, there is generally substantial test cost and test time associated with ensuring the proper memory operation. This test cost and test time translate into an increase in system cost and a decrease in system performance.
There are a number of memory test methodologies that employ either external test hardware, embedded self-test logic (“MBIST”), or both. However, the usefulness of these test methodologies is limited due to the high cost and other limitations associated with them. For instance, external test hardware such as automatic test equipment (“ATE”) is very expensive. Moreover, the development time and cost associated with implementing MBIST is relatively high. These costs and limitations are especially significant when testing dynamic random access memory (“DRAM”). For example, technological developments, such as increases in DRAM speed, may require manufacturers to upgrade ATE machines relatively frequently. In addition, MBIST in DRAM chips generally cannot be fully utilized for system level testing of memory boards.
Because of the increasing cost, complexity, and time involved with fully testing DRAM chips, DRAM manufacturers often provide “effectively tested” (“ETT”) DRAM chips to memory module manufacturers at a lower price rather than providing fully tested DRAM chips. Memory module manufacturers often prefer the ETT DRAM chips mainly due to their greater availability. Memory module manufacturers who receive ETT DRAM chips then have to assume a part of the responsibility of validating the DRAM chips, adding to the complexity of the memory module test process.